1. Field of Use
This invention relates to data processing systems and more particularly to a data processing system which includes a cache unit for facilitating the processing of requests for instructions and operands.
2. Prior Art
As is well known in the art, many data processing systems each include a main store and a cache unit positioned between the system's data processing unit and main store for the purpose of increasing the performance of such data processing unit. Additionally, such high performance data processing units have included instruction buffers for providing fast access to instructions.
It has been recognized that even with a cache unit and instruction buffer, data processing unit's performance can be compromised by the transfer from one instruction sequence to a second instruction sequence. To overcome this, one prior art system includes an instruction buffer capable of storing two instruction sequences which can be available for use by the data processing unit. For further information regarding this system, reference may be made to the copending patent application "An Instruction Buffer Associated with a Cache Memory Unit", invented by John E. Wilhite, et al, bearing Ser. No. 866,083, filed on Dec. 30, 1977 and assigned to the same assignee as named herein.
While the above arrangement facilitates the transfer from one instruction sequence to another, it requires that execution of the command specifying the fetching of the instructions of one sequence be completed before the command for fetching instructions of a second sequence is issued to main store. During that time, the processing unit is required to halt its operation. The cache unit, upon loading all of the instructions of a block into the instruction buffer started the processing unit up in parallel with issuing the next command to fetch a second block of instructions.
Even in the case where it would be possible to issue the above sequence of commands for fetching first and second blocks of instructions in succession without interrupting the operation of the processing unit, it would still be necessary to halt operations until the execution of both commands had been completed before issuing another command for fetching instructions.
Accordingly, in either case, there would be a substantial decrease in the processing unit's performance.
Accordingly, it is a primary object of the present invention to provide an improved cache system.
It is a further object of the present invention to provide a cache arrangement which permits a high degree of overlap of commands specifying the fetching of instruction blocks from a main store.
It is still a further object of the present invention to provide a cache arrangement which facilitates the processing of commands generated by a processing unit in response to transfer or branch type instructions.